Titlebook: Asynchronous System-on-Chip Interconnect; John Bainbridge Book 2002 John Bainbridge 2002 Asynchronous.Hardware.Integrated ciruits.Intercon

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ECG769

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Malfunction

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Asynchronous Design,This chapter provides an introduction to asynchronous design. The information presented here is intended to set the context for the overlap of two themes: asynchronous design and SoC interconnect, in the form of an asynchronous macrocell bus. Further details on all aspects of asynchronous design are available elsewhere [85].

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The Physical (Wire) Layer,A shared bus is a collection of wires where all interfaces to the wires comply with an ordered protocol devised to avoid deadlocks and data corruption. In the layered bus implementation hierarchy of Figure 4.1 these wires collectively form the lowest layer, the physical layer.

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Protocol Layer,The link layer discussed in Chapter 5 provides (one or more) multipoint connections allowing information to be routed between senders and receivers, where these need not be the same from one communication to the next.

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Transaction Layer,This chapter addresses the uppermost level of the communication hierarchy of an on-chip bus, the transaction layer.