Titlebook: Architecture of Computing Systems -- ARCS 2013; 26th International C Hana Kubátová,Christian Hochberger,Bernhard Sick Conference proceeding

同步左右

https://doi.org/10.1007/978-3-0348-8570-6estimation of the impact of thermal coupling in determining the appropriate status from a thermal stand-point. The presented approach is based on two stages: off-line characterization of the target architecture estimates thermal coupling coefficients, that will be used at run-time for proper DTM dec

动脉

Hyperbolic Equations of Nonscalar Typea was collected using an x86 ASIM-based performance simulator from Intel Labs. The data shows that the new architecture improves performance of a 2-wide out-of-order x86 processor core by an average of 4.2%, while saving 43% of the energy consumption of the reorder buffer and retirement register fil

含糊

Running Time Analysis: Switch Analysisplement concurrency, reactivity, and control flow in SystemJ. Experimental evaluation over a range of benchmarks shows significant performance improvements over the existing platforms developed for the execution of the SystemJ program.

旧石器时代

Algorithms for Intelligent Systemsficient utilization of the cache space. Experimental evaluation of ACR technique for 2-core and 4-core systems using SPEC CPU 2000 and 2006 benchmark suites shows significant speed-up improvement over the . and . techniques.

Harrowing

Václav Větvička Ph. D.,Petr Šíma Ph. D.ware brings important benefits in terms of execution time as well as energy consumption with respect to traditional commit protocols that use the general-purpose interconnection network . Additionally, our proposal has negligible requirements in terms of area. Results for a 16-core CMP show that the

痛苦一下

Exploiting Thermal Coupling Information in MPSoC Dynamic Thermal Management,estimation of the impact of thermal coupling in determining the appropriate status from a thermal stand-point. The presented approach is based on two stages: off-line characterization of the target architecture estimates thermal coupling coefficients, that will be used at run-time for proper DTM dec

Fresco

Virtual Register Renaming,a was collected using an x86 ASIM-based performance simulator from Intel Labs. The data shows that the new architecture improves performance of a 2-wide out-of-order x86 processor core by an average of 4.2%, while saving 43% of the energy consumption of the reorder buffer and retirement register fil

expunge

GALS-CMP: Chip-Multiprocessor for GALS Embedded Systems,plement concurrency, reactivity, and control flow in SystemJ. Experimental evaluation over a range of benchmarks shows significant performance improvements over the existing platforms developed for the execution of the SystemJ program.

landmark

想象

Deploying Hardware Locks to Improve Performance and Energy Efficiency of Hardware Transactional Memware brings important benefits in terms of execution time as well as energy consumption with respect to traditional commit protocols that use the general-purpose interconnection network . Additionally, our proposal has negligible requirements in terms of area. Results for a 16-core CMP show that the