Titlebook: Applied Reconfigurable Computing; 11th International S Kentaro Sano,Dimitrios Soudris,Pedro C. Diniz Conference proceedings 2015 Springer I

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Makarand M. Ghangrekar,Bikash R. Tiwariration as well as run-time reconfiguration of applications and their mapping require detailed introspection of the dynamic effects on the target platform. Additionally, extra-functional properties like power consumption and performance characteristics are important metrics to assess the quality of a

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Nishant K. Srivastava,R. C. Tripathin space exploration for dynamically reconfigurable systems. Besides, a middleware to extend the capability of TLM introducing a semantic to interconnect components described at different abstraction levels or languages is added. This middleware allows to automate the creation of the corresponding co

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Makarand M. Ghangrekar,Bikash R. Tiwari run-time dynamic hardware multithreading. The architecture uses on-chip networking to interconnect routers and computational elements providing a flexible and highly configurable structure. Quadratic routers are reducing total router count while ensuring short communication paths and minimal resour

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ArchHDL: A Novel Hardware RTL Design Environment in C++ing based on C++. The key features of this language are that (1) designers describe a combinational circuit as a function and (2) the ArchHDL library implements non-blocking assignment in C++. Using these features, designers are able to write a hardware in a Verilog HDL-like style. The source code o

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Dynamic Memory Management in Vivado-HLS for Scalable Many-Accelerator Architecturesramework with the industrial strength Vivado-HLS tool, and we evaluate its effectiveness with a set of key accelerators from emerging application domains. DMM-HLS delivers significant increase in FPGA’s accelerators density (3.8. more accelerators) in exchange for affordable overheads in terms of de