Titlebook: Analog Circuit Design; RF Analog-to-Digital Rudy J. Plassche,Hohan H. Huijsing,Willy Sansen Book 1997 Springer Science+Business Media Dordr

Arrhythmia

Power and Scaling Rules of CMOS High-Speed A/D Convertersign of the A/D converter in the same technology is to be preferred. A/D converters based on a folding architecture are capable to fulfill the increasing demand for performance to such embedded A/D converters. This paper describes CMOS technology directions and trends related to the performance of fo

吃掉

An Embedded 170-mW 10-Bit 50-MS/s CMOS ADC in 1-mm2le-metal, single-poly CMOS process, the circuit measures 1.4-mm × 1.4-mm including a bandgap and a S&H, while the ADC itself occupies 1-mm.. At a conversion rate of 50-MS/s the untrimmed ADC dissipates 170-mW and exhibits 54-dB S/ (N+D) with a 12-MHz 90% full-scale input.

高度

expound

A 12 bit, 50 MSample/s Cascaded Folding & Interpolating ADCand Interpolating architecture. The ADC is optimized for digital telecommunication applications. The integrated Track & Hold circuit enables SNR > 66 dB and THD < 72 dB, measured over an input signal bandwidth of 70 MHz. The ADC is realized in a 13 GHz, 1 μm BiCMOS process and measures 7 mm., while

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