Titlebook: Analog Circuit Design; Sensor and Actuator J. H. Huijsing,Michiel Steyaert,Arthur Roermund Book 2004 Springer Science+Business Media New Y

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O. A. Essich,H. Schönian,G. Brandstäterold buffer in which voltage multiplication is replaced by voltage addition. An experimental 12-bit 3.3 MS/s algorithmic ADC in 0.25.m standard CMOS for a 2V application is described. It occupies O.15mm. of die area and dissipates 5.5mW. The power and area FOMs are well below those previously reported for 1.5-bit algorithmic ADC stages.

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Multi-Sensor Interfacesd interface units in a single-chip solution. In this article, the requirements to realize such multi-sensor interface chips are discussed. The main focus is on the analog frontend and the system architecture of the chip.

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CMOS Sensor Interface Arrays for DNA Detectionlectrochemical operation principle of the chip. Stability and accuracy aspects are considered in detail. Measured data are shown from electrical characterizations as well as from biological experiments.

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Power Management Solutions for Desktop and Mobile CPUS, the ADOPT. voltage positioning technology, maintaining high efficiency over a wide loadcurrent range, current and thermal balancing, current-sense solutions, protection functions, functional block schematics of VRM control ICs, and challenges for the IC designers.

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Design of Class-D Audio Power Amplifiers in Soi TechnologyRobustness is complicated by high voltages and the switching of large currents in the output stage. Further the output stage needs to be robust against all sorts of fault conditions such as short circuits and electro-static discharge.