期刊全称 | Advanced ASIC Chip Synthesis | 期刊简称 | Using Synopsys® Desi | 影响因子2023 | Himanshu Bhatnagar | 视频video | | 图书封面 |  | 影响因子 | .Advanced ASIC Chip Synthesis: Using Synopsys® Design..Compiler® Physical Compiler® and PrimeTime®,Second. .Edition. describes the advanced concepts and techniquesused towards ASIC chip synthesis, physical synthesis, formalverification and static timing analysis, using the Synopsys suite oftools. In addition, the entire ASIC design flow methodology targetedfor VDSM (Very-Deep-Sub-Micron) technologies is covered in detail..The emphasis of this book is on real-time application of Synopsystools, used to combat various problems seen at VDSM geometries.Readers will be exposed to an effective design methodology forhandling complex, sub-micron ASIC designs. Significance is placed onHDL coding styles, synthesis and optimization, dynamic simulation,formal verification, DFT scan insertion, links to layout, physicalsynthesis, and static timing analysis. At each step, problems relatedto each phase of the design flow are identified, with solutions andwork-around described in detail. In addition, crucial issues relatedto layout, which includes clock tree synthesis and back-endintegration (links to layout) are also discussed at length.Furthermore, the book contains in-depth discussions on the bas | Pindex | Book 2002Latest edition |
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