| 书目名称 | The Power of Assertions in SystemVerilog |
| 编辑 | Eduard Cerny,Surrendra Dudani,Dmitry Korchemny |
| 视频video | |
| 概述 | Explains the new SystemVerilog 1800-2009 LRM enhancements.Includes practical examples that address underlying performance issues.Provides deep understanding needed for successful deployment of the ful |
| 图书封面 |  |
| 描述 | This book is the result of the deep involvementof the authors in the development of EDA tools, SystemVerilog Assertion standardization, and many years of practical experience. One of the goals of this book is to expose the oral knowhow circulated among design and veri?cation engineers which has never been written down in its full extent. The book thus contains many practical examples and exercises illustr- ing the various concepts and semantics of the assertion language. Much attention is given to discussing ef?ciency of assertion forms in simulation and formal veri?- tion. We did our best to validate all the examples, but there are hundreds of them and not all features could be validated since they have not yet been implemented in EDA tools. Therefore, we will be grateful to readers for pointing to us any needed corrections. The book is written in a way that we believe serves well both the users of SystemVerilog assertions in simulation and also those who practice formal v- i?cation (model checking). Compared to previous books covering SystemVerilog assertions we include in detail the most recent features that appeared in the IEEE 1800-2009 SystemVerilog Standard, in particular th |
| 出版日期 | Book 20101st edition |
| 关键词 | ABV; Assertion Based Verification; Debugging; HDL; Hardware Verification Languages; Sequences; Simulation; |
| 版次 | 1 |
| doi | https://doi.org/10.1007/978-1-4419-6600-1 |
| copyright | Springer Science+Business Media, LLC 2010 |
发表于 2025-3-21 18:34:23
