Titlebook: Silicon Semiconductor Technology; Processing and Integ Ulrich Hilleringmann Textbook 20231st edition The Editor(s) (if applicable) and The

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书目名称Silicon Semiconductor Technology影响因子(影响力)




书目名称Silicon Semiconductor Technology影响因子(影响力)学科排名




书目名称Silicon Semiconductor Technology网络公开度




书目名称Silicon Semiconductor Technology网络公开度学科排名




书目名称Silicon Semiconductor Technology被引频次




书目名称Silicon Semiconductor Technology被引频次学科排名




书目名称Silicon Semiconductor Technology年度引用




书目名称Silicon Semiconductor Technology年度引用学科排名




书目名称Silicon Semiconductor Technology读者反馈




书目名称Silicon Semiconductor Technology读者反馈学科排名

MAIZE

https://doi.org/10.1007/978-3-658-41041-4Processing of Silicon; CMOS Circuit Integration; Silicon on Insulator; Dry Etching; Ion Implantation; Che

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苦笑

Sedative

Synchronism

Silicon Wafer Production,s. Starting from quarzite as the raw silicon material, purification and crystallization enable the growth of perfect monocrystalline ingots. They are cut into discs, getting perfect surfaces by subsequent grinding, etching and polishing.

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Oxidation of Silicon,y oxide layers grow in dry or wet oxygen atmosphere at high temperature using silicon from the substrate, leading to segregation effects and interface charges. Alternatively, silicon dioxide deposition apply physical or chemical deposition techniques.

Aqueous-Humor

Deposition Process, low concentration of impurities. These layers should be deposited stress-free at the lowest possible temperature on all other materials used in semiconductor technology. The techniques developed for these purposes can be divided into chemical and physical deposition.

使闭塞

Metallization and Contacts,a chip by conductor tracks. As the work function of p- and n-type silicon differ, an appropriate metal is needed for ohmic contacts to the doped electrodes. Aluminium exhibits limited stability at high current density, thus copper wires are used in modern microprocessors.

抚慰

MOS Technologies for Circuit Integration,cuits. Simple PMOS and NMOS metal gate processes for field effect transistor integration are explained first. The transistion to self-aligned polysilicon gate processes for minimum feature sizes down to 1.5 µm enables higher switching frequencies, whereas the CMOS technique reduces the power consumption of integrated circuits.