Titlebook: Scanning Probe Lithography; Hyongsok T. Soh,Kathryn Wilder Guarini,Calvin F. Q Book 2001 Springer Science+Business Media New York 2001 Lei

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Scanning Probe Tips for SPL,eld-induced oxidation and electron exposure SPL, probe tips must be electrically conductive and sharp to enable field concentration at the tip apex. For field emission of electrons from the tips, the workfunction of the tip material is significant. In the case of feedback control of the emitted curr

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Scanning Probe Arrays for Lithography,le large-scale patterning technology. For example, a writing speed of 10 mm/s and a pixel size of 100 nm correspond to a pixel rate of 100 kHz (kilopixels per second). An exposure field measuring 1 cm × 1 cm contains 10. pixels. If we raster scanned the tip over every pixel in the exposure field, it

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On-Chip Lithography Control,antly from the setpoint. In place of this feedback circuitry, we integrated a transistor current source onto the cantilever chip to control the electron exposure dose delivered to the resist. In this chapter we describe the design, fabrication, and operation of this integrated current source.

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SPL by Electric-Field- Enhanced Oxidation,in hydroflouric acid (HF). Then the tip of a scanning probe with a voltage bias (typically a few volts) is brought to the vicinity of the surface creating an intense electric field. The magnitude of this electric field can be in excess of 1 V/nm. A schematic diagram of the experimental set up is shown in Fig. 2.1.

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Critical Dimension Patterning Using SPL,he gate is critical for device electrical performance and yield. Gate patterning is performed after significant device processing. Therefore the feature must be accurately aligned to the previously patterned regions. It must also be written over the sample topography created by the prior fabrication steps.

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High Speed Resist Exposure With a Single Tip,age of a direct write approach is that it does not require expensive and time-consuming mask fabrication. SPL may also have superior alignment capabilities. Nevertheless, in order for SPL to become a viable technology for high-resolution semiconductor lithography, the throughput must be dramatically increased.