| 书目名称 | Routing Congestion in VLSI Circuits | | 副标题 | Estimation and Optim | | 编辑 | Prashant Saxena,Rupesh S. Shelar,Sachin S. Sapatne | | 视频video | | | 概述 | Provides an in-depth treatment of routing congestion in VLSI circuits.Comprehensively surveys the work done and points to challenges for the future.Equips readers with the knowledge to prudently choos | | 丛书名称 | Integrated Circuits and Systems | | 图书封面 |  | | 描述 | With dramatic increases in on-chip packing densities, routing congestion has become a major problem in integrated circuit design, impacting convergence, performance, and yield, and complicating the synthesis of critical interc- nects. The problem is especially acute as interconnects are becoming the performance bottleneck in modern integrated circuits. Even with more than 30% of white space, some of the design blocks in modern microprocessor and ASIC designs cannot be routed successfully. Moreover, this problem is likely to worsen considerably in the coming years due to design size and technology scaling. There is an inherent tradeo? between choosing a minimum delay path for interconnect nets, and the need to detour the routes to avoid “tra?c jams”; congestion management involves intelligent allocation of the available int- connect resources, up-front planning of the wire routes for even distributions, and transformations that make the physical synthesis ?ow congestion-aware. The book explores this tradeo? that lies at the heart of all congestion m- agement, in seeking to address the key question: how does one optimize the traditional design goals such as the delay or the area of a | | 出版日期 | Book 2007 | | 关键词 | Computer-Aided Design (CAD); Routing; Sapatnekar; VLSI; VLSI circuits; estimation; integrated circuit; metr | | 版次 | 1 | | doi | https://doi.org/10.1007/0-387-48550-3 | | isbn_softcover | 978-1-4419-4013-1 | | isbn_ebook | 978-0-387-48550-8Series ISSN 1558-9412 Series E-ISSN 1558-9420 | | issn_series | 1558-9412 | | copyright | Springer-Verlag US 2007 |
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发表于 2025-3-21 17:18:55
