| 书目名称 | Layout Optimization in VLSI Design | | 编辑 | Bing Lu,Ding-Zhu Du,Sachin S. Sapatnekar | | 视频video | | | 丛书名称 | Network Theory and Applications | | 图书封面 |  | | 描述 | Introduction The exponential scaling of feature sizes in semiconductor technologies has side-effects on layout optimization, related to effects such as inter connect delay, noise and crosstalk, signal integrity, parasitics effects, and power dissipation, that invalidate the assumptions that form the basis of previous design methodologies and tools. This book is intended to sample the most important, contemporary, and advanced layout opti mization problems emerging with the advent of very deep submicron technologies in semiconductor processing. We hope that it will stimulate more people to perform research that leads to advances in the design and development of more efficient, effective, and elegant algorithms and design tools. Organization of the Book The book is organized as follows. A multi-stage simulated annealing algorithm that integrates floorplanning and interconnect planning is pre sented in Chapter 1. To reduce the run time, different interconnect plan ning approaches are applied in different ranges of temperatures. Chapter 2 introduces a new design methodology - the interconnect-centric design methodology and its centerpiece, interconnect planning, which consists of p | | 出版日期 | Book 2001 | | 关键词 | Standard; VLSI; integrated circuit; layout; metal-oxide-semiconductor transistor; modeling; optimization; s | | 版次 | 1 | | doi | https://doi.org/10.1007/978-1-4757-3415-7 | | isbn_softcover | 978-1-4419-5206-6 | | isbn_ebook | 978-1-4757-3415-7Series ISSN 1568-1696 | | issn_series | 1568-1696 | | copyright | Springer Science+Business Media Dordrecht 2001 |
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发表于 2025-3-21 16:18:50
