| 书目名称 | High Level Synthesis of ASICs under Timing and Synchronization Constraints |
| 编辑 | David C. Ku,Giovanni Micheli |
| 视频video | |
| 丛书名称 | The Springer International Series in Engineering and Computer Science |
| 图书封面 |  |
| 描述 | Computer-aided synthesis of digital circuits from behaviorallevel specifications offers an effective means to deal with increasingcomplexity of digital hardware design. .High Level Synthesis ofASICs. .Under Timing and Synchronization Constraints. addressesboth theoretical and practical aspects in the design of a high-levelsynthesis system that transforms a behavioral level description ofhardware to a synchronous logic-level implementation consisting oflogic gates and registers. ..High Level Synthesis of ASICs Under Timing and Synchronization..Constraints. addresses specific issues in applying high-levelsynthesis techniques to the design of ASICs. This complements previousresults achieved in synthesis of general-purpose and signalprocessors, where .data-path. design is of utmost importance. Incontrast, ASIC designs are often characterized by complex.control. schemes, to support communication and synchronizationwith the environment. The combined design of efficient data-pathcontrol-unit is the major contribution of this book. .Three requirements are important in modeling ASIC designs:.concurrency, external synchronization., and .detailed timing..constraints.. The objective of the res |
| 出版日期 | Book 1992 |
| 关键词 | ASIC; Hardware; Signal; algorithms; communication; complexity; computer; integrated circuit; logic; model; mod |
| 版次 | 1 |
| doi | https://doi.org/10.1007/978-1-4757-2117-1 |
| isbn_softcover | 978-1-4419-5129-8 |
| isbn_ebook | 978-1-4757-2117-1Series ISSN 0893-3405 |
| issn_series | 0893-3405 |
| copyright | Springer Science+Business Media New York 1992 |
发表于 2025-3-21 17:04:12
