| 书目名称 | Generating Hardware Assertion Checkers | | 副标题 | For Hardware Verific | | 编辑 | Marc Boulé,Zeljko Zilic | | 视频video | | | 概述 | Efficient synthesis of assertion checkers for the main assertion languages (PSL and SVA).Applications in verification, emulation, post-fabrication debugging, on-line monitoring, with a unique “under-t | | 图书封面 |  | | 描述 | .Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity...This is the first book that presents an “under-the-hood” view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement.. | | 出版日期 | Book 2008 | | 关键词 | Emulator; Hardware; assertion checkers; assertion-based verification; automata; hardware verification; int | | 版次 | 1 | | doi | https://doi.org/10.1007/978-1-4020-8586-4 | | isbn_softcover | 978-90-481-7922-0 | | isbn_ebook | 978-1-4020-8586-4 | | copyright | Springer Science+Business Media B.V. 2008 |
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发表于 2025-3-21 17:07:38
