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Titlebook: Embedded Systems: Design, Analysis and Verification; 4th IFIP TC 10 Inter Gunar Schirner,Marcelo Götz,Franz J. Rammig Conference proceeding

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书目名称Embedded Systems: Design, Analysis and Verification
副标题4th IFIP TC 10 Inter
编辑Gunar Schirner,Marcelo Götz,Franz J. Rammig
视频video
概述State-of-the-art research.Fast-track conference proceedings.Unique visibility
丛书名称IFIP Advances in Information and Communication Technology
图书封面Titlebook: Embedded Systems: Design, Analysis and Verification; 4th IFIP TC 10 Inter Gunar Schirner,Marcelo Götz,Franz J. Rammig Conference proceeding
描述This book constitutes the refereed proceedings of the 4th IFIP TC 10 International Embedded Systems Symposium, IESS 2013, held in Paderborn, Germany, in June 2013. The 22 full revised papers presented together with 8 short papers were carefully reviewed and selected from 42 submissions. The papers have been organized in the following topical sections: design methodologies; non-functional aspects of embedded systems; verification; performance analysis; real-time systems; embedded system applications; and real-time aspects in distributed systems. The book also includes a special chapter dedicated to the BMBF funded ARAMIS project on Automotive, Railway and Avionics Multicore Systems.
出版日期Conference proceedings 2013
关键词formal verification; model checking; open hardware; performance evaluation; system-on-chip
版次1
doihttps://doi.org/10.1007/978-3-642-38853-8
isbn_softcover978-3-642-43028-2
isbn_ebook978-3-642-38853-8Series ISSN 1868-4238 Series E-ISSN 1868-422X
issn_series 1868-4238
copyrightIFIP International Federation for Information Processing 2013
The information of publication is updating

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978-3-642-43028-2IFIP International Federation for Information Processing 2013
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Embedded Systems: Design, Analysis and Verification978-3-642-38853-8Series ISSN 1868-4238 Series E-ISSN 1868-422X
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,Metrik – Definition und Begriffsabgrenzung,a specification capturing core algorithms. Algorithm development itself largely occurs in Algorithm Design Environments (ADE) with little or no hardware concern. Currently, algorithm and system design environments are disjoint; system level specifications are manually implemented which leads to the
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