| 书目名称 | Design Automation for Timing-Driven Layout Synthesis |
| 编辑 | Sachin S. Sapatnekar,Sung-Mo Kang |
| 视频video | |
| 丛书名称 | The Springer International Series in Engineering and Computer Science |
| 图书封面 |  |
| 描述 | Moore‘s law [Noy77], which predicted that the number of devices in tegrated on a chip would be doubled every two years, was accurate for a number of years. Only recently has the level of integration be gun to slow down somewhat due to the physical limits of integration technology. Advances in silicon technology have allowed Ie design ers to integrate more than a few million transistors on a chip; even a whole system of moderate complexity can now be implemented on a single chip. To keep pace with the increasing complexity in very large scale integrated (VLSI) circuits, the productivity of chip designers would have to increase at the same rate as the level of integration. Without such an increase in productivity, the design of complex systems might not be achievable within a reasonable time-frame. The rapidly increasing complexity of VLSI circuits has made de- 1 2 INTRODUCTION sign automation an absolute necessity, since the required increase in productivity can only be accomplished with the use of sophisticated design tools. Such tools also enable designers to perform trade-off analyses of different logic implementations and to make well-informed design decisions. |
| 出版日期 | Book 1993 |
| 关键词 | CMOS; VLSI; algorithms; automation; circuit; design automation; interconnect; layout; modeling; optimization; |
| 版次 | 1 |
| doi | https://doi.org/10.1007/978-1-4615-3178-4 |
| isbn_softcover | 978-1-4613-6393-4 |
| isbn_ebook | 978-1-4615-3178-4Series ISSN 0893-3405 |
| issn_series | 0893-3405 |
| copyright | Springer Science+Business Media New York 1993 |
发表于 2025-3-21 16:11:28
