Titlebook: Code Optimization Techniques for Embedded Processors; Methods, Algorithms, Rainer Leupers Book 2000 Springer Science+Business Media Dordrec

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https://doi.org/10.1007/978-981-10-7116-4he data path with functional units (FUs) and a local register file. Such a data path architecture is frequently found in multimedia processors and ASIPs. We will focus on the problem of instruction scheduling. Fig. 4.1 shows how this phase relates to the overall compilation flow.

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expository

啜泣

Code Selection for Multimedia Processors,In this chapter we consider the problem of mapping a machine-independent intermediate representation into assembly code for multimedia processors. Fig. 5.1 shows the position of this code selection problem in the compilation flow.

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cogitate

Introduction,an integration scale more than one order of magnitude higher than in today’s microelectronics. For the high performance processor segment, even larger integration scales have been predicted, with processor performance reaching 3 million MIPS by the year 2010 [Tech00].

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Performance Optimization with Conditional Instructions,tures of embedded processors. In contrast, this chapter describes a largely machine-independent code optimization technique, which primarily works on the intermediate representation (IR) level of the compilation flow (fig. 6.1).