Titlebook: Architecture of Computing Systems - ARCS 2017; 30th International C Jens Knoop,Wolfgang Karl,Thilo Pionteck Conference proceedings 2017 Spr

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Fault-Tolerant Execution on COTS Multi-core Processors with Hardware Transactional Memory Support Hardware enhancements to further increase the applicability of the approach are proposed and evaluated with SPEC CPU 2006 benchmarks. The resulting performance overhead is 47% on average, assuming the existence of the proposed hardware support.

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Exploring ILP and TLP on a Polymorphic VLIW Processor can adapt its issue-width during runtime. By design, the processor can be perceived as a single wide core (8-issue VLIW) or two medium-wide cores (4-issue) or four small cores (2-issue) that can run high-ILP/low DLP, medium-ILP/medium DLP, and low-ILP/high-DLP applications, respectively. Furthermor

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https://doi.org/10.1007/978-1-4899-3487-1m the ground up having reliability as a major concern. Both operating systems were evaluated through extensive neutron-beam testings on a 28 nm ARM-based state-of-the-art system-on-chip, and their fault tolerance mechanisms reached reductions in the overall cross-sections relative to their baselines

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