Novice
发表于 2025-3-21 17:13:26
书目名称Defect and Fault Tolerance in VLSI Systems影响因子(影响力)<br> http://figure.impactfactor.cn/if/?ISSN=BK0264718<br><br> <br><br>书目名称Defect and Fault Tolerance in VLSI Systems影响因子(影响力)学科排名<br> http://figure.impactfactor.cn/ifr/?ISSN=BK0264718<br><br> <br><br>书目名称Defect and Fault Tolerance in VLSI Systems网络公开度<br> http://figure.impactfactor.cn/at/?ISSN=BK0264718<br><br> <br><br>书目名称Defect and Fault Tolerance in VLSI Systems网络公开度学科排名<br> http://figure.impactfactor.cn/atr/?ISSN=BK0264718<br><br> <br><br>书目名称Defect and Fault Tolerance in VLSI Systems被引频次<br> http://figure.impactfactor.cn/tc/?ISSN=BK0264718<br><br> <br><br>书目名称Defect and Fault Tolerance in VLSI Systems被引频次学科排名<br> http://figure.impactfactor.cn/tcr/?ISSN=BK0264718<br><br> <br><br>书目名称Defect and Fault Tolerance in VLSI Systems年度引用<br> http://figure.impactfactor.cn/ii/?ISSN=BK0264718<br><br> <br><br>书目名称Defect and Fault Tolerance in VLSI Systems年度引用学科排名<br> http://figure.impactfactor.cn/iir/?ISSN=BK0264718<br><br> <br><br>书目名称Defect and Fault Tolerance in VLSI Systems读者反馈<br> http://figure.impactfactor.cn/5y/?ISSN=BK0264718<br><br> <br><br>书目名称Defect and Fault Tolerance in VLSI Systems读者反馈学科排名<br> http://figure.impactfactor.cn/5yr/?ISSN=BK0264718<br><br> <br><br>
完成
发表于 2025-3-22 00:03:12
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意见一致
发表于 2025-3-22 02:32:35
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Afflict
发表于 2025-3-22 05:33:40
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Dendritic-Cells
发表于 2025-3-22 09:32:54
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江湖郎中
发表于 2025-3-22 15:28:34
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江湖郎中
发表于 2025-3-22 19:23:14
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PLIC
发表于 2025-3-23 00:26:26
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HAIL
发表于 2025-3-23 05:00:34
CRT-Pacing Only Versus CRT-DefibrillatorA large number of reconfiguration schemes have been presented for defect tolerant mesh arrays. Here a number of such schemes will be compared. Area and speed based measures are presented, along with a summary of the methods required to estimate area overhead, processor utilization, yield and speed.
kindred
发表于 2025-3-23 06:28:22
The Effect on Yield of Clustering and Radial Variations in Defect DensityThis work examines the effect on yield, of the clustering and radial variation of fatal defects. An expression is developed for fatal defects as a function of chip area and distance of the chip from the edge of the wafer, and used to estimate the yield of successively larger numbers of array segments of a bipolar SRAM.