黄油没有 发表于 2025-3-30 08:13:10
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http://reply.papertrans.cn/87/8690/868978/868978_52.png闹剧 发表于 2025-3-30 17:44:31
FPGA Implementation of TTC and OBC for a Cubesat,to design and launch a student satellite in Low Earth Orbit and perform on-orbit operations to demonstrate the imaging of the Earth’s surface, high-altitude operations and de-orbiting maneuver. The Telemetry, Tracking and Telecommand (TTC) and On-Board Computer (OBC) subsystem implementation allow t最有利 发表于 2025-3-30 22:39:30
Thermal Management Scheme for SWIR IDDCA Used in Space Payloads,gement while isolating the IDDCA assembly from the external vibrations and loads. The scheme is validated through implementation on the actual IDDCA & measuring the change in temperature w.r.to time at critical locations.miscreant 发表于 2025-3-31 01:27:35
Hardware and Simulation Comparison of Synchronous Buck Topology for Hi-Rel Applications,help of a simulation software LT-Spice and compared with the hardware test results. High voltage synchronous and current mode controlled Integrated Chip IC is used with external MOSFETs. In addition to efficiency Load regulation of <1% and Output ripple voltage of <1% is achieved in this design.压碎 发表于 2025-3-31 06:00:48
http://reply.papertrans.cn/87/8690/868978/868978_56.png鞠躬 发表于 2025-3-31 12:41:45
Design and Implementation of High Frequency Single Output Forward Converter for Space Application,tion along with the input voltage feed forward technique. Lossless snubber is incorporated to improve the core reset process. Converter efficiency is greater than 75% at full load. Inhibition and protection circuits are incorporated. The complete converter is also realized using hybrid microcircuit technology in addition to PCB.cogent 发表于 2025-3-31 15:12:14
http://reply.papertrans.cn/87/8690/868978/868978_58.png抚慰 发表于 2025-3-31 20:39:13
FPGA Implementation of TTC and OBC for a Cubesat, the satellite mission. The use of FPGA in space missions provides high computational power, and parallel processing at relatively lower power consumption. Telemetry encoder and telecommand decoder are implemented in HDL Verilog, and simulation is conducted in the Vivado design suite for Xilinx Zynq 7000 FPGA.