方舟 发表于 2025-3-23 10:41:54

Applications of Hierarchical Verification in Model Checkingms to successfully verify a wide spectrum of large and complex circuits. This paper describes a variety of the decomposition techniques that we have used as part of a large industrial formal verification effort on the Intel Pentium® 4 (Willamette) processor.

dialect 发表于 2025-3-23 16:42:53

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微不足道 发表于 2025-3-23 20:46:31

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Infect 发表于 2025-3-23 23:58:47

Efficient Reachability Analysis and Refinement Checking of Timed Automata Using BDDs timed automata [.]. Matrix-based algorithms for the reachability analysis of timed automata are implemented in tools like Kronos, Uppaal, HyTech and Rabbit. A new BDD-based version of Rabbit, which supports also refinement checking, is now available.

BRUNT 发表于 2025-3-24 05:32:51

Deriving Real-Time Programs from Duration Calculus SpecificationsThe main idea of our approach is to model discretization at state level by introducing the discrete states approximating the continuous ones, and then derive a specification of the control program over discrete states. Then the control program is derived from its specification using an extension of

懦夫 发表于 2025-3-24 08:10:03

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轿车 发表于 2025-3-24 13:00:32

Formally-Based Design Evaluation Logic in Lotos - the ISO Language Of Temporal Ordering Specification). Relations for (strong) conformance are defined to verify a design specification against a high-level specification. Tools have been developed for automated testing and verification of conformance between an implementation and it

Detain 发表于 2025-3-24 17:01:36

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带来的感觉 发表于 2025-3-24 19:54:01

Register Transformations with Multiple Clock Domainsance and power requirements. In this paper, we identify a special case of multiple clocking that encompasses typical design styles, and we present a theory enabling a wide range of register transformations relating to the multiple clock domains. For example, we can perform pipelining, phase abstract

有毛就脱毛 发表于 2025-3-25 00:24:49

Temporal Properties of Self-Timed Ringst self-timed networks, a ring, and note that for timing applications, self-timed rings should maintain uniform spacing of events. In practice, all previous designs of which we are aware cluster events into bursts. In this paper, we describe a dynamical systems approach to verify the temporal propert
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查看完整版本: Titlebook: Correct Hardware Design and Verification Methods; 11th IFIP WG 10.5 Ad Tiziana Margaria,Tom Melham Conference proceedings 2001 Springer-Ver