Arb853 发表于 2025-3-23 12:02:59
http://reply.papertrans.cn/24/2306/230558/230558_11.pngOverthrow 发表于 2025-3-23 15:36:50
Carrier Phase Based Attitude Determination Using Tightly Coupled BDS/INSure the attitude in a high precision were designed. Last, a platform was set up for testing the effectiveness of the algorithm with a single-frequency BDS receiver and an inertial sensor. The results show that the algorithm can effectively improve the measurement accuracy and output frequency of the attitude.刀锋 发表于 2025-3-23 18:09:29
Research and Implementation of the DDR2-Based Shared Memory Switch Fabric for Onboard Switchesey resources consumption can meet the requirements of triple modular redundancy. When the data is 64 bit wide and the system clock is 100 MHz, the peak throughput of the switch fabric can reach 6.4 Gbps.paleolithic 发表于 2025-3-24 00:42:09
http://reply.papertrans.cn/24/2306/230558/230558_14.png乐意 发表于 2025-3-24 06:24:26
ACO-GA Combined Algorithm for Solving Spectrum Allocation Problem in D2D Communicationssed. This algorithm combines ant colony algorithm and modified genetic algorithm based on the theory of graph coloring. Simulation results show that ACO-GA combined algorithm performs superior than traditional ant colony algorithm and genetic algorithm on spectrum efficiency and interference cost.emission 发表于 2025-3-24 08:03:11
http://reply.papertrans.cn/24/2306/230558/230558_16.pngpainkillers 发表于 2025-3-24 14:11:53
http://reply.papertrans.cn/24/2306/230558/230558_17.png材料等 发表于 2025-3-24 17:59:33
https://doi.org/10.1007/978-3-663-11382-9slice lookup tables while used in a 16 . 16 switch fabric, which can meet the requirements of triple modular Redundancy. The scheme can meet the requirements of 160 Gbps switch fabric with 16, 10 Gbps ports, and the design is implemented in a Xilinx xc6vlx240t FPGA. Typical simulated results are presented to show the availability of the scheme.bronchodilator 发表于 2025-3-24 21:32:49
,Ausführung von Solargeneratoren,mproves the system reliability and the ability of recovery from failure. The iSLIP algorithm with the function of load balancing is used in a 16 . 16 CIOQ switch, and the whole switch fabric is implemented in a Xilinx xc7vx690t FPGA. Typical simulated results are given and analysized.离开 发表于 2025-3-25 02:42:43
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