recession
发表于 2025-4-1 02:29:40
Low Power and High-Speed Full Adder with Complemented Logic and Complemented XOR Gaterry are proposed in this paper. The proposed designs are efficient in power and performance. Complemented logic is used to design sum and carry outputs that require less number of transistors. A novel XNOR cell has been designed for generating the sum and carry outputs. T-spice simulations are carri