Anthrp
发表于 2025-3-25 05:39:21
High performance distributed object systems, problem of designing a software component architecture that extends the current emerging desktop object composition models to the domain of high performance networks and massively parallel compute servers.
Creatinine-Test
发表于 2025-3-25 08:00:00
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LUDE
发表于 2025-3-25 14:16:20
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陈旧
发表于 2025-3-25 16:35:41
High-performance computing and applications in image processing and computer vision,d computer vision. Most image processing algorithms can readily exploit SIMD (Single Instruction, Multiple Data Stream) machine architectures. The mapping of these algorithms to such machines is rather straightforward. The fine granularity parallelism and regular data units are inherent in the natur
confederacy
发表于 2025-3-25 21:52:22
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assail
发表于 2025-3-26 03:58:05
Evaluation of multithreaded processors and thread-switch policies,or on-line transaction processing systems. It considers the effect of switching threads on cache misses in a two-level cache system. It also examines several different thread-switch policies. The results suggest that multithreading with a small number (3–5) of active threads can significantly improv
死猫他烧焦
发表于 2025-3-26 07:21:11
A multithreaded implementation concept of prolog on Datarol-II machine,s introduced which was developed for implementing Prolog on massively parallel computers. The Logicflow is a dataflow-like graph in which nodes are macro dataflow nodes and tokens represent macrothreads. The Datarol-II architecture efficiently supports both the management of macrothreads derived fro
IRK
发表于 2025-3-26 11:56:31
Thread Synchronization Unit (TSU): A building block for high performance computers, architectures built with control-flow (i.e. commodity) microprocessors. The TSU design is based on the Decoupled Data-Driven model of execution. This model decouples the synchronization from the computation portions of a program and allows them to execute asynchronously. At compile time a program i
gonioscopy
发表于 2025-3-26 13:32:35
Data dependence path reduction with tunneling load instructions,er to hide the load latency, and thus reduces the length of the data dependence path. True data dependences can not be removed by any techniques such as register renaming, and are the unavoidable obstacle limiting the instruction level parallelism. The length of the data dependence path including th
Lamina
发表于 2025-3-26 19:48:50
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