artless
发表于 2025-3-23 12:22:54
Loop Termination Predictionictors into smaller loops that may be effectively captured. Our results show that for many programs adding a small loop termination buffer can reduce the missprediction rate by up to a difference of 2%.
以烟熏消毒
发表于 2025-3-23 17:44:52
http://reply.papertrans.cn/43/4263/426290/426290_12.png
使人烦燥
发表于 2025-3-23 18:55:59
Conference proceedings 2000two great successes with ISHPC’97 (Fukuoka, November 1997) and ISHPC’99 (Kyoto, May 1999), many people have requested that the symposium would be held in the capital of Japan and we have agreed. I am very pleased to serve as Conference Chair at a time when high p- formance computing (HPC) has a sign
6Applepolish
发表于 2025-3-23 23:06:00
Limits of Task-based Parallelism in Irregular Applicationsreceding code when there is a high probability of independence. We estimate the amount of STP in irregular applications by measuring the number of memory-independent instructions these tasks expose. We find that 7 to 22% of dynamic instructions are within memory-independent tasks, depending on assumptions.
Progesterone
发表于 2025-3-24 04:57:29
Skewed Data Partition and Alignment Techniques for Compiling Programs on Distributed Memory Multicommplex programs with minimized data communication than that of the dimension-ordered scheme. Finally, the experimental results show that our proposed scheme has more opportunities to align data arrays such that data communications over processors can be minimized.
出价
发表于 2025-3-24 09:51:02
http://reply.papertrans.cn/43/4263/426290/426290_16.png
一再困扰
发表于 2025-3-24 11:02:20
Processor Mechanisms for Software Shard Memorycks, hardware translation of memory addresses to home processors, fast detection of remote accesses, and dedicated thread slots for shared-memory handlers. These mechanisms have been implemented on the MAP processor, and allow remote memory references to be completed in as little as 336 cycles at low hardware cost.
人充满活力
发表于 2025-3-24 17:38:47
Macroservers: An Object-Based Programming and Execution Model for Processor-in-Memory Arrayseatures for specifying the distribution and alignment of data in virtual object space, the binding of threads to data, and a future-based synchronization mechanism. We provide a number of motivating examples and give a short overview of implementation considerations.
Limited
发表于 2025-3-24 20:48:38
Blue Geneo not require huge amounts of memory. Such problems can be found in computational biology, high-end visualization, computational fluid dynamics, and other areas. This talk will be primarily about the Blue Gene hardware and system software. We will also briefly discuss the protein folding application
牵连
发表于 2025-3-25 00:44:39
The Case for Speculative Multithreading on SMT Processors architecture in which spare thread contexts are used to support the DMT execution of procedure and loop threads. We show two significant advantages of this approach: (1) it increases processor utilization and total execution throughput when few programs are running, and (2) it eliminates or reduces