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,Reduction of Interconnect Delay and Resistance While Minimizing Grid Area in GNR-Based VLSI Routingn be bent only in ., ., and . angles. Hence, the routing of GNR is different than that of traditional VLSI routing and may require extra grid area. In this paper, we propose an algorithm for the construction of global routing tree using GNR-based interconnect to reduce the interconnect delay and interconnect resistance with minimized grid area.