多话
发表于 2025-3-21 17:58:41
书目名称Computer Engineering and Technology影响因子(影响力)<br> http://impactfactor.cn/if/?ISSN=BK0233536<br><br> <br><br>书目名称Computer Engineering and Technology影响因子(影响力)学科排名<br> http://impactfactor.cn/ifr/?ISSN=BK0233536<br><br> <br><br>书目名称Computer Engineering and Technology网络公开度<br> http://impactfactor.cn/at/?ISSN=BK0233536<br><br> <br><br>书目名称Computer Engineering and Technology网络公开度学科排名<br> http://impactfactor.cn/atr/?ISSN=BK0233536<br><br> <br><br>书目名称Computer Engineering and Technology被引频次<br> http://impactfactor.cn/tc/?ISSN=BK0233536<br><br> <br><br>书目名称Computer Engineering and Technology被引频次学科排名<br> http://impactfactor.cn/tcr/?ISSN=BK0233536<br><br> <br><br>书目名称Computer Engineering and Technology年度引用<br> http://impactfactor.cn/ii/?ISSN=BK0233536<br><br> <br><br>书目名称Computer Engineering and Technology年度引用学科排名<br> http://impactfactor.cn/iir/?ISSN=BK0233536<br><br> <br><br>书目名称Computer Engineering and Technology读者反馈<br> http://impactfactor.cn/5y/?ISSN=BK0233536<br><br> <br><br>书目名称Computer Engineering and Technology读者反馈学科排名<br> http://impactfactor.cn/5yr/?ISSN=BK0233536<br><br> <br><br>
saphenous-vein
发表于 2025-3-21 21:41:46
Hardware Architecture for the Parallel Generation of Long-Period Random Numbers Using MT Methody pseudo-random number generators(PRNG) based on binary linear recurrences. In this paper, a hardware architecture for the generation of parallel long-period random numbers using MT19937 method was proposed. Our design is implemented on a Xilinx XC6VLX240T FPGA device and is capable of producing mul
Modify
发表于 2025-3-22 00:28:58
MGTE: A Multi-level Hybrid Verification Platform for a 16-Core Processoringly important. In this paper, a multi-level hybrid verification platform called MGTE is designed and developed for a 16-core processer PX-16. MGTE supports software simulating and hardware emulating in module level, sub-system level or full-chip level, which is capable of verifying the processor d
脆弱带来
发表于 2025-3-22 04:50:16
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poliosis
发表于 2025-3-22 11:20:19
A Study of Cache Design in Stream Processor processor and it aims at exploiting the parallelism and locality of the applications. In this paper, first, we inspect the memory access characteristics of FT64 with cache and without cache. Second, we propose an improved cache design method. Making use of the feature of stream data type used by FT
帽子
发表于 2025-3-22 13:07:36
Design and Implementation of Dynamically Reconfigurable Token Coherence Protocol for Many-Core Procency (like snoopy protocol) or not depending on bus-like interconnects (like directory protocol). Recently, Token Coherence has been proposed to capture the main characteristic of traditional protocols. However, since Token Coherence relies on broadcast-based transient request and inefficient persist
帽子
发表于 2025-3-22 21:00:23
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Desert
发表于 2025-3-22 21:25:58
ADL and High Performance Processor Designessor design, lots of institutes and companies use ADL as processor quick prototype design language and use it to generate processor simulator, test-benches and compiler utilities. This paper analyzes and compares three processor description languages. We also give the disadvantages of modern ADL wh
弄污
发表于 2025-3-23 03:42:43
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Abutment
发表于 2025-3-23 06:06:14
A Hardware Implementation of Nussinov RNA Folding Algorithmarallelism of this kind of algorithms is one of the most relevant areas in computational biology. In this paper, we propose a parallel way to implement the Nussinov algorithm on hardware. We implement our work on Xilinx FPGA, the total clock cycles to accomplish the algorithm is about half of using